(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for testing failing bits of DRAM devices during chip probe testing.
(2) Description of the Prior Art
Data storage or memory devices that are extensively applied in the semiconductor technology are the Dynamic Random Access Memory (DRAM) and the Static Random Access Memory (SRAM) chips. A single DRAM cell stores a bit of data on a capacitor as an electrical charge and typically consists of a single Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for data access and a single capacitor for data storage. Continuing reduction in device feature size results, for these storage cells, in serious limitations of increased data storage capability. The process technology in the manufacturing of SPAM and DRAM devices has, during the last several decades, migrated from 0.8 μm 4M memories to 0.18 μm 256M memories with a continuing decrease in memory cell size and concurrent increase in memory capacity. DRAM devices continue to be used heavily since these devices require less substrate surface space than comparable devices.
Current semiconductor devices are being operated at continuously increasing speed, the operational speed of memory chips must in therefore also be increased. This places increased demands on the testing of the memory devices, the development of faster testers results in more expensive methods of testing the memory devices. To enhance memory device throughput, memory chips need to be tested while these chips are still part of a wafer. The testing of memory chips is aimed at testing for failing chips, memory chips that pass this test are at the same time sorted in accordance with the performance of the device.
U.S. Pat. No. 6,237,115 (Ting et al.) provides a design for testability in very high-speed memory cells. This invention provides for a test circuit that is formed on a high speed memory chip to allow performance testing of the memory chip that is still part of a wafer or that has been packaged. A low speed tester can be used in this manner, reducing the cost impact of the testing operation. The test circuit creates a timing delay that is used as a reference for testing.
U.S. Pat. No. 5,896,399 (Lattimore et al.) provides a system and method for testing self-timed memory arrays by allowing some parts of the array to use a Static Evaluation technique. The array area and the timing of the array are not affected by the testing and can therefore continue to function under normal conditions. Functions and data may become pseudo-static at the first part of the clock cycle.
U.S. Pat. No. 6,230,292 (Duesman et al.) provides for methods of testing memory devices during the writing and reading of test information to and from the memory cells. Operational parameters of the device are controllably adjusted in an effort to imbalance or alter the voltage differential that is observed on the bit lines. The response of the sense amplifier, by incorrectly sensing the intended test information that is stored in the memory cells, indicates a defect in the memory device.
The invention detects fail bits of a DRAM cell during chip probe testing, in this manner saving test time and accurately detecting failing bits and providing a means for repairing the memory device at the time of chip probing. The column select (CSL) and word line (WL) pulses are under the instant invention self-time controlled, allowing emulating DRAM operation for different operating conditions.
U.S. Pat. No. 6,237,112 (Ting et al.) discloses a test circuit on a high-speed memory chip for performance testing the chip on a low speed tester. The test circuit creates a timing delay that is used as a reference for testing of the memory chip.
U.S. Pat. No. 5,896,399 (Lattimore et al.) describes a self-timed memory array test method. Functions and data may become pseudo-static during the first part of the clock cycle.
U.S. Pat. No. 6,230,292 (Duesman et al.) teaches methods for testing the cell margin in memory devices. Critical voltages and timings may be manipulated to test cell performance.